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CY2212
Direct RambusTM Clock Generator (Lite)
Features
* Direct RambusTM clock support * High-speed clock support * Input Select option * Crystal Oscillator Divider Output * Output edge-rate control * 16-pin TSSOP
Benefits
* One pair of differential output drivers * 400-MHz maximum, 300-MHz minimum output frequency * PLL multiplier select * LCLK = XTAL/2, not driven by phase-locked loop (PLL) * Minimize EMI * Space-saving, low-cost package
Logic Block Diagram
XIN XOUT CLK CLKB
Xtal Oscillator
PLL xM
S /2 LCLK
Xtal Value = 18.75 MHz
Pin Configuration
16-pin TSSOP
TOP VIEW
VDDP VSSP XOUT XIN VDDL LCLK VSSL NC 1 2 3 16 15 14 S VDD VSS CLK CLKB VSS VDD NC
CY2212
4 5 6 7 8
13 12 11 10 9
Frequency Select Table
S 0 1 M (PLL Multiplier) 16 64/3 CLK,CLKB 300 MHz 400 MHz LCLK 9.375 MHz 9.375 MHz
Cypress Semiconductor Corporation Document #: 38-07466 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 12, 2005
CY2212
Pin Description
Name VDDP VSSP XOUT XIN VDDL LCLK VSSL NC NC VDD VSS CLKB CLK VSS VDD S Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description 3.3V Power Supply for PLL Ground for PLL Reference Crystal Feedback Reference Crystal Input 1.8V Power Supply for LCLK LVCMOS Output, x1/2 Crystal Frequency Ground for LCLK No Connect (Reserved for Test Mode) No Connect (Reserved for Test Mode) 3.3V Power Supply Ground Output Clock (complement), Connect to Rambus Channel Output Clock, Connect to Rambus Channel Ground 3.3V Power Supply PLL Multiplier Select Input, Pull-up Resistor Internal
Absolute Maximum Conditions
Parameter VDD,ABS VI, ABS VIL, ABS Description Max. voltage on VDD, VDDP, or VDDL with respect to ground Max. voltage on any pin with respect to ground Max. voltage on LCLK with respect to ground Min. -0.5 -0.5 -0.5 Max. 4.0 VDD + 0.5 VDDL + 0.5 Unit V V V
Crystal Requirements
These are the requirements for the recommended crystal to be used with the CY2212 DRCG Lite clock source. The crystal load capacitance is internally set to 11 pF. Parameter XF XFTOL XEQRES XTEMP XDRIVE XMI XIR XSAR XOS
Notes: 1. At 25C 3C. 2. CL = 10 pF. 3. -10C to 75C. 4. At XF 500 kHz.
Description Frequency Frequency Tolerance[1] Equivalent Resistance Temperature Drift[3] Drive Level Motional Inductance Insulation Resistance Spurious Attenuation Ratio[4] Overtone Spurious
[2]
Min. 14.0625 -15
Max. 18.75 15 100 10
Unit MHz ppm ppm W mH M dB dB
0.01 20.7 500 3 8
1500 25.3
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CY2212
DC Electrical Specifications
Parameter VDD VDDL TA VIL VIH RPUP Supply voltage LCLK supply voltage Ambient operating temperature Input signal low voltage at pin S Input signal high voltage at pin S Internal pull-up resistance Description Min. 3.04 1.7 0 - 0.65 10 Max. 3.56 2.1 70 0.35 - 100 Unit V V C VDD VDD k
AC Electrical Specifications
Parameter fXTAL,IN CIN,CMOS CXTAL Description
Input frequency at crystal input[5] Input capacitance at S pin[6] Crystal load capacitance
Min.
14.0625 - -
Typ.
- - 11
Max.
18.75 10 -
Unit
MHz pF pF
DC Device Specifications
Parameter VCM VX VCOS VCOH VCOL rOUT VLOH VLOL Description
Differential output common-mode voltage Differential output crossing-point voltage Output voltage swing (p-p single-ended)[7] Output high voltage Output low voltage Output dynamic resistance (at pins)[8] LCLK Output high voltage at IOH = -10 mA LCLK Output low voltage at IOL = 10 mA
Min.
1.35 1.25 0.4 - 1.0 12 VDDL - 0.45V 0
Max.
1.75 1.85 0.7 2.1 - 50 VDDL 0.45
Unit
V V V V V V V
State Transition Characteristics
Specifies the maximum settling time of the CLK, CLKB, and LCLK outputs from device power-up. For VDD, VDDP, and VDDL any sequences are allowed to power-up and power-down the CY2212 DRCG-Lite. From To Transition Latency 3 ms Description Time from VDD/VDDL/VDDP is applied and settled to CLK/CLKB/LCLK outputs settled VDD/VDDL/VDDP On CLK/CLKB/LCLK Normal
AC Device Specifications
Parameter tCYCLE tJ tJL DC tDC,ERR Clock cycle time Jitter over 1-6 clock cycles at 400 MHz[9] Jitter over 1-6 clock cycles at 300 Long-term jitter at 400 MHz Long-term jitter at 300 MHz Long-term average output duty cycle Cycle-cycle duty cycle error at 400 MHz Cycle-cycle duty cycle error at 300 MHz
Notes: 5. Nominal condition with 18.75-MHz crystal. 6. Capacitance measured at Freq = 1 MHz, DC Bias = 0.9 V, and VAC < 100 mV. 7. VCOS = VOH - VOL. 8. rOUT = VO/ IO. This is defined at the output pins, not at the measurement point of Figure 3. 9. Output short-term jitter specification is peak-peak and defined in Figure 10.
Description
Min. 2.5 - - - - 45% - -
Max. 3.33 100 140 300 400 55% 50 70
Unit ns ps ps ps ps tCYCLE ps ps
MHz[9]
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CY2212
AC Device Specifications (continued)
Parameter tCR, tCF tCR, CF BWLOOP tCYCLE,L tLR, tLF tJC,L tJ10,L DCL Description Output rise and fall times (measured at 20%-80% of output voltage) Difference between output rise and fall times on the same pin of a single device (20%-80%) PLL loop bandwidth LCLK clock cycle time LCLK output rise and fall time LCLK cycle jitter
[10]
Min. 250 - 50 kHz (-3 dB) 106.6 - -0.8 40% RSL Clock Output Driver
Max. 500 100 8 MHz (-20 dB) 142.2 1 0.8 60%
Unit ps ps
ns ns ns ns tCYCLE,L
LCLK 10-cycle jitter[10,11] LCLK output duty cycle
-1.1 * tJC,L 1.1 * tJC,L
Functional Specifications
This section gives the detailed functional specifications of the device physical layer. These specifications refer to the logical and physical interfaces. Crystal Input The CY2212 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are given on page 3 of this data sheet. Select Input There is only one select input, pin S. This pin selects the frequency multiplier in the PLL, and is a standard LVCMOS input. The S pin has an internal pull-up resistor. The multiplier selection is given on page 1 of this data sheet. LCLK Output Driver In addition to the Rambus clock driver outputs, there is another clock output driver. The LCLK driver is a standard LVCMOS output driver. Figure 1 below shows the LCLK output driver load circuit.
Figure 2 shows the clock driver equivalent circuit. Measurement Point RT = ZCH Differential Driver RS RP RP RS S ZCH RT = ZCH ZCH
Measurement Point Figure 2. Equivalent Circuit The differential driver has a low output impedance in the range of about 20 ohms. The driver also produces a specified voltage swing on the channel. The nominal value of the channel impedance, ZCH, is 28 ohms. Series resistor RS and parallel resistor RP are used to set the voltage swing on the channel. The driver output characteristics are defined together with the external components, and the output clock is specified at the measurement point indicated in Figure 2. The complete set of external components for the output driver, including edge-rate filter capacitors required for system operation, are shown in Figure 3. The values for the external components are given in Table 1. The output clocks drive transmission lines, potentially long lines. Since circuit board traces will act as lossy, imperfectly terminated transmission lines with some discontinuities, there will be reflections generated which will travel back to the DRCG-Lite output driver. If the output impedance does not match ZCH, secondary reflections will be generated that will add to position-dependent timing uncertainty. Therefore, the CY2212 not only provides proper output voltage swings, but also provides a well-matched output impedance. The driver impedance, ROUT, is in series with RS, and the combination is in parallel with RP. The clock driver is specified as a black-box at the packaged pins. The output characteristics are measured after the series resistance, RS. The outputs are terminated differentially, with no applied termination voltage.
LCLK 10 pF
120 120
Figure 1. LCLK Test Load Circuit
Notes: 10. LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period as defined on page 8. 11. LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter as defined on page 8.
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CY2212
Figure 3 below shows the clock driver implemented as a push-pull driver. When stimulating the output driver, the transmission lines shown in Figure 3 can be replaced by a direct connection to the termination resistors, RT. The values for the external components are given in Table 1. As mentioned previously, the clock driver's output impedance matches the channel impedance. To accomplish this, each of the output driver devices are sized to have an ROUT of about 20 ohms when fully turned on. ROUT is the dynamic output resistance, and is defined in the DC Device Characteristics Table on page 3 of this data sheet. Since ROUT is in series with RS, and that combination is in parallel with RP, the effective output impedance is given by: RP(RS + ROUT)/(RP + RS + ROUT). This calculation results in a effective output impedance of about 27 ohms for the values listed in Table 1. Since the total impedance is dominated by the external resistors, a large possible range of ROUT is allowed. When the output is transitioning, the impedance of the CMOS devices increases dramatically. The purpose of RP is to limit the maximum output impedance during output transitions. In order to control signal attenuation and EMI, clock signal rise/fall times must be tightly controlled. Therefore, external filter capacitors CF are used to control the output slew rate. In addition, the capacitor CMID is used to provide AC ground at the mid-point of the RP resistors. Table 1 gives the nominal values of the external components and their maximum acceptable tolerance, assuming ZCH = 28 ohms.
CF RS DRCG Lite
Measurement Point RT =ZCH RP RP CMID ZCH CMID ZCH Measurement Point RT =ZCH
RS CF
Figure 3. Output Driver Table 1. Output External Component Values Parameter RS RP CF CMID Description Series Resistor Parallel Resistor Edge-rate Filter Capacitor AC Ground Capacitor Value 68 39 15 0.01 Tolerance 5% 5% 10% 20% Unit ohm ohm pF F
Measurement Point RX CF RS DRCG Lite RP CMID RP RX RS CF RX Measurement Point ZCH ZCH RX ZCH ZCH
RT = ZCH
CMID RT = ZCH RT = ZCH
CMID RT = ZCH
Figure 4. Output Driving Two Channels
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CY2212
Dual-Channel Output Driver
Figure 4 shows the clock driver driving two high-impedance channels. The purpose of the series resistors RX is to decouple the two channels, and prevent noise from one channel from coupling onto the second channel. With ZCH = 40 ohms and the series resistor set to RX = 16 ohms, the channel becomes an effective 56-ohm channel. The two channels in parallel can be treated as a single 28-ohm channel, and all of the external component values listed in Table 1 can be used. and 80% points of the voltage swing, with the swing defined as VH - VL. For example, the output voltage swing VCOS = VOH - VOL. The device parameters defined according to Figure 5 are as follows. Table 2. Definition of Device Parameters Parameter VOH, VOL VCOS VCM VIH, VIL tCR, tCF tCR, CF Definition Clock output high and low voltages Clock output swing VCOS = VOH - VOL Common-mode voltage VCM = (VOH - VOL)/2 Vdd LVCMOS input high and low voltages Clock output rise and fall times Clock output rise/fall time delta tCR,CF = tCR - tCF
Signal Waveforms
A physical signal that appears at the pins of the device is deemed valid or invalid depending on its voltage and timing relations with other signals. This section defines the voltage and timing waveforms for the input and output pins of the CY2212. The Device Characteristics tables list the specifications for the device parameters that are defined here. Input and Output voltage waveforms are defined as shown in Figure 5. Both rise and fall times are defined between the 20%
VOH
80%
V(t)
20%
tCF tCR
VOL
Figure 5. Voltage Waveforms
CLK
Vx+ Vx,nom Vx- Figure 6. Crossing-point Voltage Figure 6 shows the definition of output crossing point. The nominal crossing point between the complementary outputs is defined to be at the 50% point of the DC voltage levels. There are two crossing points defined, Vx+ at the rising edge of CLK and Vx- at the falling edge of CLK. For some clock waveforms, both Vx+ and Vx- might be below Vx, nom (for example, if tCR is larger than tCF). Vx is defined as the differential output crossing point voltage. Figure 7 shows the definition of long-term duty cycle, which is simply the waveform high-time divided by the cycle time (defined at the crossing point). Long-term duty cycle is the average over many (>10,000) cycles. Short-term duty cycle is defined in the next section. DC is defined as the output clock long-term duty cycle.
CLKB
Jitter
This section defines the specifications that relate to timing uncertainty (or jitter) of the input and output waveforms. Figure 8 shows the definition of long-term jitter with respect to the falling edge of the CLK signal. Long-term jitter is the difference between the minimum and maximum cycle times. Equal requirements apply for rising edges of the CLK signal. tJL is defined as the output long-term jitter.
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CY2212
CLK
CLKB
tPW+ tCYCLE
DC = tPW + /tCYCLE
Figure 7. Duty Cycle
CLK
CLKB
tCYCLE
tJL = tCYCLE,max - tCYCLE,min over 10000 cycles
Figure 8. Long-term Jitter
CLK
CLKB
tCYCLE,i tCYCLE,i+1
tJ = tCYLCE,i - tCYCLE,i + 1 over 10000 consecutive cycles
Figure 9. Cycle-to-cycle Jitter Figure 9 shows the definition of cycle-to-cycle jitter with respect to the falling edge of the CLK signal. Cycle-to-cycle jitter is the difference between cycle times of adjacent cycles. Equal requirements apply for rising edges of the CLK signal. tJ is defined as the clock output cycle-to-cycle jitter. Figure 10 shows the definition of four-cycle short-term jitter. Short-term jitter is defined with respect to the falling edge of the CLK. Four-cycle short-term jitter is the difference between the cumulative cycle times of adjacent four cycles. Equal requirements apply for rising edges of the CLK signal. Equal requirements also apply for two-cycle short-term jitter and three-cycle short-term jitter, and for five-cycle short-term jitter and six-cycle short-term jitter. tJ is defined as the clock output short-term jitter over 2, 3, 4, 5, or 6 cycles. The purpose of this definition of short-term jitter is to define errors in the measured time (for example, t4CYCLE,i) vs. the expected time. The purpose for measuring the adjacent time t4CYCLE, i+1 is only to help determine the expected time for t4CYCLE, i. Alternate methods of determining tJ are possible, including comparing the measured time to an expected time based on a local cycle time, tCYCLE,LOCAL. This local cycle time could be determined by taking the rolling average of a group of cycles (5-10 cycles) preceding the measured cycles. However, it is important to differentiate this rolling average from the average cycle time, tCYCLE,AVG, which is the average cycle time over the 10,000 cycles. Using a long-term average instead of a rolling average would define tJ as a long-term jitter instead of a short-term jitter, and would normally giver overly pessimistic results. Figure 11 shows the definition of cycle-to-cycle duty cycle error. Cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles. Equal requirements apply to the low-times. tDC,ERR is defined as the clock output cycle-to-cycle duty cycle error.
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CY2212
CLK
CLKB
t4CYCLE,i
t4CYCLE,i+1
tJ = t4CYCLE,i - t4CYCLE,i+1 over 10000 consecutive cycles
Figure 10. Short-term Jitter
CLK
Cycle i
Cycle i+1
CLKB
tPW+,i+1 tCYCLE,i+1 tCYCLE,i+1 tPW+,i
tDC,ERR = tPW+,i - tPW+,i+1
Figure 11. Cycle-to-cycle Duty Cycle Error
LCLK
T 10*T Figure 12. LCLK Jitter Figure 12 shows the definition of LCLK cycle jitter and LCLK 10-cycle jitter. These parameters apply to the LCLK output, and not to the Rambus channel clock outputs. LCLK cycle jitter is the variation in the clock period, T, over a continuous set of clock cycles. The difference between the maximum period and the nominal period in the set of clock cycles measured would be compared to the max spec listed in the AC Device Characteristics Table on page 3. LCLK cycle jitter is measured between rising edges at 50% of the output voltage, and is measured continuously over 30,000 cycles. LCLK 10-cycle jitter is the variation in the time of 10 clock cycles, 10*T, where T is the clock period. The difference between the maximum 10-cycle period and the nominal 10-cycle period in the set of clock cycles measured would be compared to the max spec listed in the AC Device Characteristics Table on page 5. Note that the specification for LCLK 10-cycle jitter is defined based on the measured value of LCLK cycle jitter. LCLK 10-cycle jitter is measured between the first rising edge and the tenth rising edge at 50% of the output voltage, and is measured over 30,000 continuous cycles. tJC,L is defined as the LCLK output cycle jitter, and tJ10,L is defined as the LCLK output jitter over 10 cycles.
Measurement
The short-term jitter specification (over one to six cycles) for the clock source is given as tJ, as previously shown. Jitter should be measured using a jitter measurement system that has the flexibility of measuring cycle-to-cycle jitter as a function of cycle count. It is important that the short-term jitter be measured over consecutive cycles in order to prevent long-term drift from causing overly pessimistic results. When measured over 10,000 consecutive cycles, the short-term jitter measurements generate large amounts of data which can be viewed in a histogram. Figure 13 shows an example histogram of data from a 4-cycle short-term jitter measurement, with results that are within spec lines for tJ. Note that the jitter is specified as peak-to-peak, so the center of the histogram need not be exactly zero. Further details of jitter measurement methodologies are given in the Rambus DRCG-Lite Specification Appendix A published by Rambus, Inc.
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CY2212
4 Cycle Jitter Jitter Spec Figure 13. Example Jitter Measurement Histogram
Ordering Information
Ordering Code CY2212ZC-2 CY2212ZC-2T Lead-Free CY2212ZXC-2 CY2212ZXC-2T 16-lead TSSOP 16-lead TSSOP-Tape and Reel Commercial Commercial 16-lead TSSOP 16-lead TSSOP-Tape and Reel Package Type Operating Range Commercial Commercial
Package Drawing and Dimensions
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027]
51-85091-*A
4.90[0.193] 5.10[0.200]
0.09[[0.003] 0.20[0.008]
Rambus, RDRAM, and the Rambus Logo are registered trademarks of Rambus Inc. Direct Rambus, RIMM, SORIMM, and Direct RDRAM are trademarks of Rambus, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2212
Document History Page
Document Title: CY2212 Direct RambusTM Clock Generator (Lite) Document Number: 38-07466 REV. ** *A ECN NO. 117801 308300 Issue Date 12/10/02 See ECN Orig. of Change CKN RGL Description of Change New Data Sheet Corrected Ordering Info from -1 to -2 Added Lead Free Devices (-2) Added CXTAL specs in the AC Electrical specifications table
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